A semiconductor wafer is typically composed of a substrate, such as a silicon wafer, on which a plurality of transistors have been formed. Transistors are chemically and physically connected into a substrate and are interconnected through the use of well-known multilevel coplanar interconnects to form functional circuits. Typical multilevel interconnects are comprised of stacked thin-films consisting of, for example, one or more of the following: titanium (Ti), titanium nitrate (TiN), copper (Cu), aluminum (Al), tungsten (W), tantalum (Ta), cobalt (Co), ruthenium (Ru), or any combination thereof.
The traditional technique for forming functional multilevel coplanar interconnects has involved planarizing the surface of the interconnects via chemical-mechanical polishing (CMP). CMP involves the concurrent chemical and mechanical polishing of an overlying first layer to expose the surface of a non-planar second layer on which the first layer has been formed (see, e.g., U.S. Pat. Nos. 4,671,851; 4,910,155; 4,944,836; 6,592,776; 7,524,347; and 8,518,135).
CMP processes typically involve a polishing composition (also referred to as a polishing slurry) that contains abrasive particles, such as silica or alumina, in an acidic or basic solution. In a typical CMP process, a wafer is mounted upside down on a carrier in a CMP tool. A force pushes the carrier and the wafer downward toward a polishing pad. The carrier and the wafer are rotated above the rotating polishing pad on the CMP tool's polishing table. The polishing composition is then introduced between the rotating wafer and the rotating polishing pad during the polishing process.
Although conventional CMP processes are suitable for polishing, they tend to leave undesirable contaminants on the wafer surface. In particular, the wafer surface is often contaminated with remnants of the polishing composition, such as silica or alumina abrasive particles, and with metal ions from the polishing composition and from the material being polished. Such contaminants can have an adverse effect on semiconductor wafer performance. As a result, after a polishing composition is applied to the semiconductor surface, the polishing composition typically is washed from the wafer surface with an aqueous cleaning solution after CMP is completed (see, e.g., U.S. Pat. Nos. 4,051,057; 5,334,332; 5,837,662; 5,981,454; 6,395,693; and 6,541,434 and U.S. Patent Publication 2009/0130849).
Typical post-CMP cleaning compositions have not been fully satisfactory in cleaning semiconductor wafers. For example, it has been a challenge to obtain a cleaning solution that effects both low corrosion and good cleaning of material being polished. Accordingly, there remains a need in the art for a composition and/or method to effectively clean contaminants originating from the polishing composition, the polishing pad, and the material being polished from a semiconductor surface, while also minimizing corrosion. The invention seeks to provide such a semiconductor cleaning composition. These and other advantages of the invention will be apparent from the description of the invention provided herein.